ASIC Design and Verification

Stage: Design and Verification

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ASIC Design

ASIC Verification

Definition

Activities taking place before PDR include:

· ASIC specification: Specify functional requirements of the ASIC, Create ASIC project plan
Architecture design: ASIC architecture planning and test methodology
Vendor selection (Megacells requirements)
High-level design: ASIC specifications, ASIC interface, Internal architecture (Block diagram, Partitioning,),

Activities taking place before CDR include:

High-level design: Module Definition, Module Interface

Activities taking place after CDR, before RTL (VHDL sign-off) include:

· High-level design: Module coding, Module Test, Chip integration, Chip test, Preliminary VHDL
· Megacells delivery

Activities taking place after CDR, before RTM (tape out) include:

Synthesis: from VHDL to Netlist generation
Front End: Functional verification, Automatic test generation
Back End: Release to Physical Design, Release to Layout (tape out)
After RTM, tape-out takes place, the chip is manufactured and transferred to Prototypes and Integration
ASIC verification activities are related to software only and do not concern tests performed on the chip.
Activities taking place before PDR include:

Develop full test and verification plans
Prepare verification equipment
Verify VHDL during ASIC design

Activities taking place before CDR include:

Perform various levels of verification until tape-out: Level 0: ASIC vitality test

Leve l 1: test (all) individual functions defined in architecture specifications
Level 2: test weak points as reported by designers
Level 3: random testing

Perform before tape-out unit testing and integration testing

Activities taking place after CDR include:

Perform remaining verification

Level 2: test weak points as reported by designers
Level 3: random testing

If possible, develop generic modules for re-use in the future

Note: In order to shorten TTM, it would be suitable to set-up a module library for environment objects most commonly used in projects.

Dependencies
These activities should start after the System Architecture is completed
The Design activities end at RTL before release to layout
Fabrication occurs after RTM
Vendor selection (megacells delivery, process libraries,...)
These activities should start after the System Architecture is completed and are closely linked with the ASIC Design activities
These activities continues beyond CDR as the chip is being manufactured and unit tested

Input
System architecture specifications
Architecture reference model
System architecture specifications
Architecture reference model
Design documents

Deliverables

For PDR:

General architecture, Block diagrams, Dataflow architecture, Algorithms, Detailed test plans, Check list, architecture simulation (if required)
CAD system ready
For CDR:

Model definition, Model diagram, Pinout, Programmer reference model, Block diagrams, Pseudo code, Simulation results

For PDR:

Test plans corresponding to everything being designed by ASIC designer(s) before CDR
Tools identified
For CDR:

All 4 stages of verification readyResults of before-tape-out unit and integration testing List of bugs

Responsibility
ASIC Design representative in project team ASIC Verification representative in project team

Resources

Workload

Competencies
- -

Lead-times
Front-end: 6-7 weeks
Back-end: 6-7 weeks
ASIC manufacturing: 4 weeks
-

Metrics
Coding: estimation of amount of coding done, estimation of Level 0 testing
Vendor management: readiness for next stage, timing of fixes (?)

3 types of measurements:

Specification coverage
Bugs per week (should follow Normal Distribution around peak)
# of cycles run / # of micro-seconds

Guidelines
ASIC Design-for-Test Requirements - DRAFT , ASIC Design-for-Test CHECKLIST - DRAFT , ASIC Design-for-Test Packaging Technology - DRAFT Use Specman as preferred tool whenever possible (requires a lot of manpower)
Detailed template for each review
If possible, use Quickturn to verify S/W - H/W co-simulation

.	ASIC Design	ASIC Verification
Definition	Activities taking place before PDR include: · ASIC specification: Specify functional requirements of the ASIC, Create ASIC project plan Architecture design: ASIC architecture planning and test methodology Vendor selection (Megacells requirements) High-level design: ASIC specifications, ASIC interface, Internal architecture (Block diagram, Partitioning,), Activities taking place before CDR include: High-level design: Module Definition, Module Interface Activities taking place after CDR, before RTL (VHDL sign-off) include: · High-level design: Module coding, Module Test, Chip integration, Chip test, Preliminary VHDL · Megacells delivery Activities taking place after CDR, before RTM (tape out) include: Synthesis: from VHDL to Netlist generation Front End: Functional verification, Automatic test generation Back End: Release to Physical Design, Release to Layout (tape out) After RTM, tape-out takes place, the chip is manufactured and transferred to Prototypes and Integration	ASIC verification activities are related to software only and do not concern tests performed on the chip. Activities taking place before PDR include: Develop full test and verification plans Prepare verification equipment Verify VHDL during ASIC design Activities taking place before CDR include: Perform various levels of verification until tape-out: Level 0: ASIC vitality test Leve l 1: test (all) individual functions defined in architecture specifications Level 2: test weak points as reported by designers Level 3: random testing Perform before tape-out unit testing and integration testing Activities taking place after CDR include: Perform remaining verification Level 2: test weak points as reported by designers Level 3: random testing If possible, develop generic modules for re-use in the future Note: In order to shorten TTM, it would be suitable to set-up a module library for environment objects most commonly used in projects.
Dependencies	These activities should start after the System Architecture is completed The Design activities end at RTL before release to layout Fabrication occurs after RTM Vendor selection (megacells delivery, process libraries,...)	These activities should start after the System Architecture is completed and are closely linked with the ASIC Design activities These activities continues beyond CDR as the chip is being manufactured and unit tested
Input	System architecture specifications Architecture reference model	System architecture specifications Architecture reference model Design documents
Deliverables	For PDR: General architecture, Block diagrams, Dataflow architecture, Algorithms, Detailed test plans, Check list, architecture simulation (if required) CAD system ready For CDR: Model definition, Model diagram, Pinout, Programmer reference model, Block diagrams, Pseudo code, Simulation results	For PDR: Test plans corresponding to everything being designed by ASIC designer(s) before CDR Tools identified For CDR: All 4 stages of verification readyResults of before-tape-out unit and integration testing List of bugs
Responsibility	ASIC Design representative in project team	ASIC Verification representative in project team
Resources Workload Competencies	-	-
Lead-times	Front-end: 6-7 weeks Back-end: 6-7 weeks ASIC manufacturing: 4 weeks	-
Metrics	Coding: estimation of amount of coding done, estimation of Level 0 testing Vendor management: readiness for next stage, timing of fixes (?)	3 types of measurements: Specification coverage Bugs per week (should follow Normal Distribution around peak) # of cycles run / # of micro-seconds
Guidelines	ASIC Design-for-Test Requirements - DRAFT , ASIC Design-for-Test CHECKLIST - DRAFT , ASIC Design-for-Test Packaging Technology - DRAFT	Use Specman as preferred tool whenever possible (requires a lot of manpower) Detailed template for each review If possible, use Quickturn to verify S/W - H/W co-simulation